Talk:Verilog

Not like C

a good writeup, with lots of great background info. I have one big issue with it, though: Why do folks always say that Verilog syntax is "reminiscent" of C? It looks, feels, and works almost nothing like C...

If you're comparing "VHDL vs. Verilog", it might be a workable analogy to say that's like "Pascal vs. C" in some ways, but that's where the similarity ends.

Also, the current text says that "it differs from C primarily in how the language represents literals and the ability to deal with time." Ignoring how the syntax is nothing at all like C except for begin statement-followed-by-semicolon, this completely discounts how verilog executes all top-level statements in *parallel*, which is one of the major features of any HDL.

Verilog is actually more like Pascal (from which Verilog borrows the begin ... end and the function definition styles) than it is like C. 158.140.1.25 02:56, 23 January 2007 (UTC)

Sure, some of the statements like:

 wire foo;

might look sort of like C (or a billion other languages that do declarations that way!) but most of verilog is nothing at all like C in syntax or feel. And it's not just begin/end versus curly-braces... function declaration is entirely different, switch statements use a totally different syntax and have different semantics ... and on and on ...

Anyone else have an opinion on this? I've never met anyone who *actually* thought that writing verilog was anything like writing C. Everyone pretty much parrots that verilog is "C-like" or has "C-like syntax", but when you call them on it, nobody seems to really believe it or know where they original heard that from...

I agree with you that Verilog bears only faint resemblance to C. According to what I've read, the authors of Verilog wanted a language that looked like C so it would be more familiar to engineers. It has the ternary operator, the basic math and logic operators, case sensitive variable names, and semicolon terminating (many) statements. But that's where the similarity ends. If they wanted to have it C-like they should have kept the curly brackets instead of using begin/end, kept the syntax of the switch statement, and made the declaration syntax more C like. --69.5.156.155 00:19, 10 Dec 2004 (UTC)

In example code (counter):

 :
 //enable CEP is a clock enable only
 //enable CET is a clock enable and enables the TC output
 :
 if (cet && cep) // This simulates the enables both being true

following sentences might be possibly appropriate ?

 if (cet || cep) // This simulates the enables either being true

Sinar 12:43, 27 August 2005 (UTC)

---

Can you give an example code where Verilog Resembles Pascal Code? --134.50.25.39 (talk) 16:45, 10 September 2008 (UTC)

It does look quite like Pascal, but then VHDL looks a lot like ADA (in so much as, as soon as I saw it, I thought "ADA"), where as this is more subtle. Pascal tends to use wordy syntax, the case is similar, the if/then/else construct is similar. I mean, they are different languages with different aims, obviously things are going to be slightly different. But, take for example the following:

 program Test;
  
 uses X, Y, Z; 
  
 var 
   test1: string; 
   test2: integer; 
 begin 
   test2 := get_random_number(1, 3); //get a random number between 1 and 3 
  
   //this is pretty convoluted, but we're more trying to show syntax rather than exciting code. 
   if (test2 = 1) then 
     test1 := "example"; 
   else 
     if (test2 = 2) then 
     begin 
       test1 := "convoluted"; 
     end 
   else 
     begin 
       test1 := "exciting"; 
     end; 
  
   case test2 of 
     1: do_something; //parameterless 
        break; 
     2: so_something_else(test2); //single param 
        break; 
     else 
       do_another_thing(test1, test2); //2 params 
    end; 
 end. 

This is all very "Borland dialect", but, can you see why people might draw the conclusion? It's "Pascal like" but not "Pascal based". It's more "Pascal like" that it is "C-like" to my eyes. Having said that, it also looks like the other Wirth Languages, such as Modula and Oberon, and for those two the "module" keyword is used in a very similar way also Memsom (talk) 09:34, 11 October 2011 (UTC)

---

I agree. If they wanted verilog to look like C, why did they for instance defined the "begin" and "end" instead of { and }? Why is it not the same preprocessor? Does anyone know a HDL language that really looks like C? Well, we have system-C, that that's not "similar to C", it's a library to C++, and C++ is not a HDL. I haven't use systemC, how is it to use? Is it practical to build large FPGA-project in? --Petter.kallstrom (talk) 10:36, 22 August 2009 (UTC)

Palnitkar's book[1] says "It is similar in syntax to the C programming language. Designers with C programming experience will find it easy to learn Verilog HDL". Adpete (talk) 01:44, 11 October 2013 (UTC)

Is constant section correct?

I think the binary constant example is incorrect. As I am not an expert, I have not changed the page, but I am asking the question. I believe 4'b1010 is binary 1010, 4 bits wide, decimal value 10.

207.212.81.42 23:40, 7 February 2006 (UTC)Alan]]

We need to check on the sign extension capabilities here. The example in the article states that a 20'd44 has a zero extension but what happens if I want to do a negative number? What is the default response of Verilog? Adam Arnesen (talk) 18:59, 5 June 2008 (UTC)

Links to external tools

User:Mikkalai removed all references to external tools. I see that a partial restoration has been done. However, one of the links seems more than a little dubious: "The most popular free Verilog simulator for Windows.". It is only "free" in a temporary closed-source model. Described on the vendor's website as an "evaluation version". So there are 2 issues: 1. Is it "free" and 2. what evidence is there that it is the "most popular"?

Too many examples

This page has too many god damn examples. We need a conscise summary, not a list of examples that give, by and large, an incomplete understanding of the language. Fresheneesz 07:04, 19 October 2006 (UTC)

I agree, especially in regards to the "Hello World" example. Their is no purpose in writing a "program" like the example illustrates, because Verilog is not a programming language. Yossarianisdead 04:54, 26 January 2007 (UTC)

I want to second Yossarianisdead on the "Hello World" example. When you see a "Hello World" program you immediately think programming. You would very rarely use Verilog to print Hello World. Adam Arnesen (talk) 18:54, 5 June 2008 (UTC)

Constants (literals) need not have sizes

The text and the examples give the impression that constant literals must have a bit width as part of their syntax. this is not correct. For example, 'b1010 is perfectly valid, and is distinct from 4'b1010. In fact, "10" is a perfectly valid literal even without the base.

Steveicarus 05:34, 7 January 2007 (UTC)

Yes, the text does give this impression, however, it is with good reason. If the bit width is not given, then the default is 32bits. If the base is not given, then the default is decimal. The fact that the constant literals: 'b10, 2'b10, and 10 are all different and distinct highlights the importance of using these optional fields. The only time I would think not using the bit width and or base fields would be warranted is when the intended constant literal is 32bits and or a decimal value. I believe the current text should be updated to indicate the optionality of these fields and the defaults assumed in their absence. Yossarianisdead 00:30, 17 February 2007 (UTC)

The default value is not 32 bits, but some compiler specific width more than 32 bits. In fact, I do not believe the standard says that unsized literals must have any fixed size; only that they must not be truncated to less then 32 bits.

The standard does say that "integer" variables have a fixed bit width, but again it does not say what that width is, other then that it must be at least 32 bits wide.

In any case, it is most certainly and easily verifiably obvious that explicit bit widths are not required in the syntax for literals. Steveicarus 00:50, 4 March 2007 (UTC)

Problem with History

Verilog was initialling designed as a gate level simulator not an HDL. As I recall the original LRM from Gateway contained about 24 chapters. One chapter, chapter 8 as I recall, described the constructs we currently use today as the HDL part of the language. My recollection is that Verilog became an HDL when Synopsys chose the chapter 8 constructs as the basis for their software tool, Design Compiler, to generate gates from RTL description. They didn't support VHDL until much later. Before that the chapter 8 constructs were primarily used for describing verification code to stimulate and evaluate gate level designs, a function usually referred to as a Testbench. Originally Verilog was an interpreted language, had twelve states for its logical values such as supply, strong, weak and high impedance each applied to one, zero and unknown. Very useful for old NMOS based gate level designs that often included wired-and and wired-or constructs. The original verilog primitives include and, or, nand, nor gates and even pmos and nmos transistor primitives. It also included the ability to create user defined gate level primitives via the user defined primitive (udp) feature. I believe some of these original capabilites still exist in the Verilog-XL simulator. By the way, the XL stands for "accellerated" and applied to an increase in gate level simulation performance, i.e. Cadence added an engine to the interpretor that increased the performance of simulation for those parts of a design fully described by the gate level primitives and complient udp. I also remember that prior to Verilog was a gate level simulator called ilogs, I think, that was very similar to, if not the same, as Verilog but without the chapter 8 verification constructs and maybe a couple of other features. In those days, the late 1980's, we primarily entered our digital designs using schematic editors referencing libraries of gates, flops and transistors. We ran netlistors on these graphical entries to create structural netlists that referenced Verilog primitives and udps. We added a testbench of chapter 8 code for imulation and verification. —Preceding unsigned comment added by Mgravenstein (talk • contribs) 19:57, 13 October 2008 (UTC)

I certainly concur that the name "Verilog" is for a simulator not an HDL. When I worked at Mentor in the late 80's we frequently competed against the Verilog simulator with Mentor's Quicksim. A key difference was in the creation of new gate level models. We had the QuickPart editor which used state tables to describe the behavior. The Verilog simulator used the "Verilog" language for model creation. Synopsys (much to their credit and to the bank accounts of their shareholders) realized they could synthesize hardware using that language.

Clearly, a subtle shift in naming has occurred and Verilog typically (if not exclusively) refers to the HDL these days.

I believe the primary authors of this article should cite authoritative references for the claim that the Verilog simulator authors wanted to create a "C" like language. I also agree that Verilog has very little meaningful resemblance to C.

Aspenlogic (talk) 22:27, 30 June 2010 (UTC)

I object to calling Verilog the first modern RTL. "Modern" is not a clearly defined concept, and may change in the course of the years. What is modern to us, may not be modern a generation from now.

Verilog wasn't the first RTL either. In fact, there's a clear precursor to Verilog: HiLo, developed at an UK university. My first steps with an RTL was running HiLo on a Vax, somewhere in the second half of the '80ies. When, years later, I came across Verilog, the similarity was striking, even without having been told the designer of Verilog was part of the team which developed HiLo. — Preceding unsigned comment added by 77.224.147.8 (talk) 14:31, 9 December 2013 (UTC)

Synthesizeable constructs

Is it just me or does the "Synthesizeable constructs" section say absolutely nothing about which constructs are synthesizable? Am I to assume that all examples given in that section are synthesizable? If so, what *isn't* synthesizable? I'm just embarking on learning Verilog, FWIW... 123.243.228.66 (talk) 12:28, 14 January 2009 (UTC)

I wrote the original article about synthesis - which is an important aspect of using an HDL for chip design. The examples are pretty much the MINIMUM stuff that can be synthesized. There are now-a-days a few more things that SOME synthesizers can handle - there are limited cases where "for" can be used as an example. There are some new SystemVerilog constructs that can be synthesized like "generate" but this is an article on Verilog..

The idea behind this section was to give the reader a feel for how limited the synthesizable subset is. —Preceding unsigned comment added by 64.81.240.50 (ka6s) 17:56, 22 May 2009 (UTC)

Why is it at all the case that only a subset of Verilog statements is synthesizable? I thought it is the very purpose of an HDL (as Verilog is) to automatically generate a hardware instance from a HDL "program". --Abdull (talk) 19:11, 11 February 2010 (UTC)

Because this is the subset that the synthesis tools can recognize. Put another way, this is the subset of the language that the first tool (Synopsys DC_SHELL) could deal with. There are some constructs in the language that can't possibly have hardware equivalents, such as a $display statement. Lastly. Hardware must eventually resolve to gates and flops. These constructs are the ones that describe those things directly. You build all "synthesizeable" logic from these building blocks. Ka6s (talk) 20:35, 20 March 2010 (UTC)

Concurrency?

The Overview section states that HDLs differ from programming languages in part because

HDLs add the concept of concurrency, which is parallel execution of multiple statements in explicitly specified threads...

That isn't really accurate, and seems to completely neglect programming languages like Ada, Java, occam, and Erlang that provide direct support for concurrency. --Allan McInnes (talk) 01:56, 28 June 2009 (UTC)

It's been a couple of days with no response, so I've been bold and edited the problematic sentence to remove mention of concurrency. --Allan McInnes (talk) 22:29, 29 June 2009 (UTC)

I don't know if Allan's edits have been lost in time, but he's absolutely right, and there is no discussion anywhere here or on the Verilog page about exactly what the "threading" model actually is. --70.54.233.82 (talk) 20:44, 30 October 2012 (UTC)

Signal assignment

Is it just me or did the change made by 207.38.162.22 mangle the section about signal assignment. It doesn't have anything to do with clock cycles, it has to do with what VHDL calls "delta delay", not sure if there's a term for it in Verilog.

Also, I would suggest not referring to it as "non-blocking" assignment. Non-blocking is terminology used for sequential statements that don't wait for something to happen (IO, time-passing, etc.). The = operator does not block, like <= it will execute in "zero" time. —Preceding unsigned comment added by Crazycasta (talk • contribs) 16:33, 28 July 2009 (UTC)

The correct terminology for this in the Verilog language is = (blocking), and <= (non-blocking). So these are the correct terms to use.

The statement above that "=" doesn't block is incorrect. Within a procedural block, with successive "=" clauses, the first clause will execute, and upon completion of the first clause, the next clause will execute. Consequently, the thread is "blocked" until the first clause completes.

Within a series of "<=" clauses within a procedure, all will be evaluated in parallel, i.e. one isn't evaluated before another - all have equal precedence in the current timing delta. Thus these are called "non-blocking."Ka6s (talk) 20:42, 20 March 2010 (UTC)

PLI is never deprecated, only its Access (ACC) and task/function (TF) components which are now supported withing VPI. It is more accurate to state that PLI is now based entirely on VPI routines, but VPI still is considered a component of PLI. This is what is said on IEEE-1364-2005 — Preceding unsigned comment added by Asuarez80 (talk • contribs) 17:52, 7 August 2012 (UTC)

VPI is still part of PLI.

PLI was never deprecated, the only deprecated stuff were its Access (ACC) and task/function (TF) components which are now supported withing VPI. It is more accurate to state that PLI is now based entirely on VPI routines, but VPI still is considered a component of PLI. This is what is said on IEEE-1364-2005 — Preceding unsigned comment added by Asuarez80 (talk • contribs) 17:55, 7 August 2012 (UTC)

Latest version

I noticed that the latest version displayed in the infobox is IEEE 1364-2005. In fact, IEEE 1800-2009 is a combination of both IEEE 1394-2005 (Verilog) and IEEE 1800-2005 (SystemVerilog). Should the information in the infobox updated? AlexHe34 (talk) 14:30, 15 August 2012 (UTC)

This article needs to be replaced!

This article has so many problems that I really can't see how it can be fixed. There's no discussion of the language philosophy, or of key parts of the language, and other parts are glossed over or are simply incorrect. The overview talks about "software programming languages" (?!), trots out the old nonsense about Verilog being "like C", and has a simplistic discussion of modules and 'wire'. The history is simply incorrect, and starts off with the laughably incorrect statement that Verilog was the first modern hardware description language to be invented.

The word 'net' appears 6 times, with no explanation of what it is, and no discussion of the difference between nets and registers, an absolutely fundamental part of Verilog's design philosophy (until SystemVerilog came along, anyway). There's no scheduling discussion, at all, apart from the incorrect statement that "Once an always block has reached its end, it is rescheduled (again)". No discussion of expression evaluation and the issues with it. There's an extraordinarily simplistic discussion of NBAs ("This is known as a "non-blocking" assignment. Its action doesn't register until the next clock cycle"). There's no discussion at all of (user) functions and tasks. There is no discussion of procedural statements, except to (patently incorrectly) state that Its control flow keywords (if/else, for, while, case, etc.) are equivalent [to C]. I'm sorry to have to say this, but the technical content of this article shows very little understanding of Verilog (or C), and nowhere near the level required to write a technical language article. There's no discussion of the very many issues related to the fact that the original reference for the language was actually XL, and that XL's behaviour was gradually encoded into several revisions of an LRM, and that customer requirements changed the language in the early days, and so on. There's no discussion of the many issues with the language. The only insight I could find was the rather laboured discussion of why you can't code a F/F with both an asynchronous set and reset using an "@(posedge clk or posedge reset or posedge set)" timing control, but not enough insight to see that this might imply an issue with timing controls.

The only positive thing I can say about this article is that it follows in a very long tradition of Verilog misinformation, from authors who should have known better, and users who had no other reference points.

I would offer to write an alternative, if there was any chance that it would be accepted. Is there? Who controls this article? — Preceding unsigned comment added by Elavelle100 (talk • contribs) 08:38, 26 April 2013 (UTC)

By all means correct historical information (with citations). But the article's purpose is NOT to be a manual on Verilog (See WP:NOTMANUAL). In fact there's too much description of the language in the article already. Adpete (talk) 04:53, 9 October 2013 (UTC)

Hello Elavelle100,
"Who controls this article?"

Wikipedia is a wiki. An article isn't controlled by an individual; it evolves by consensus, subject to guidelines and policies.

"I would offer to write an alternative, if there was any chance that it would be accepted. Is there?"

Improvement is good and you are welcome to try that but smaller steps are less risky. If you drop a whole new dinosaur into a working ecosystem, it might not survive, even if bigger and better than any other. The less risky alternative is to prioritize objections and revise sentences and paragraphs beginning with the worst. Regards, PeterEasthope (talk) 13:51, 24 March 2017 (UTC)

Use of the programming language infobox

The use of the programming language infobox in this article is strange, since Verilog is obviously not a programming language. The characterization of Verilog as a structured programming language is quite inaccurate as to what Verilog is. While there are procedural constructs in Verilog that could be described as being "like" the structured programming paradigm (if one reduces and ignores the facts), the majority of Verilog cannot be distorted to fit that characterization. Should that infobox simply not be used, or is it sufficiently important that some sort of infobox be present? If the latter is the case, a new infobox template specifically for hardware description and verification languages should be created and used instead. AZ1199 (talk) 11:18, 3 February 2016 (UTC)

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Problems with first example

Either the first example is wrong, or it needs more explanation:

1. If you call the module with:

  reset = true [posedge] & clock = true [posedge] -> reset only

You'd expect this condition to result in a reset and a clock.

2. If the hardware precludes the possibility of both clock and reset being posedge, the text should explain this, or the programmer ought to have commented on this to indicate it is not an error.

197.99.45.157 (talk) 05:30, 10 January 2019 (UTC)

A real piece of hardware would not give reset with clock at the same time. There is a setup/hold requirement between the two with a real flop. In fact it is often a policy in a system to remove active reset prior to starting clocks. 73.71.182.25 (talk) 11:51, 5 April 2022 (UTC)